In legacy analog imagers, particularly infrared imagers, photo-current from a detector diode is integrated by a well capacitor coupled to the detector diode, and then once per video frame, the voltage or charge of each well capacitor is transferred to a down-stream analog-to-digital converter (ADC), where the voltage is converted to a binary value. Pixel sizes continue to shrink and the ratio of well capacitor to pixel area shrinks disproportionately more. Simultaneously, there is a demand by consumers for increased Signal-to-Noise Ratio (SNR) which can be realized by increasing effective well capacitance.
In-pixel ADC imagers are used to address this problem associated with decreasing pixel size. In particular, in-pixel ADC imaging improves photo-charge capacity for infrared imaging and other applications as the size of pixels continues to decrease. A good in-pixel ADC design can store nearly all of the available photo-charge from a detector diode and thus improve SNR to near theoretical limits. A common method of integration for in-pixel ADC circuits uses a quantizing analog front end circuit which accumulates charge over a relatively small capacitor, trips a threshold and is then reset. This pattern is repeated as more photo-current integrates.
An example of an in-pixel ADC circuit 100 is illustrated in FIG. 1A. Charge from a photo-diode 110 is accumulated over an integration capacitor 115. When a threshold voltage (Vth) set by a comparator 120 and threshold voltage source 125 is reached, the circuit is reset via a reset switch 130, as discussed above. Each reset event is accumulated (counted) with a digital counter circuit 135. At each frame, a “snapshot” of the contents of the digital counter 135 is copied into a register or memory and read out, line by line. This circuit 100 operates to exponentially increase the well capacity QINT of the integration capacitor 115 by a factor of 2n, where n is the size of the digital counter 135. Thus, by conserving the available photo-charge within a frame period, this type of read-out integrated circuit 100 may achieve improved signal-to-noise ratio.
The example in-pixel ADC circuit 100 illustrated in FIG. 1A is an asynchronous circuit. In asynchronous in-pixel ADCs, the comparator reset event occurs as soon as the voltage on the integrating capacitor 115 crosses the comparator threshold. FIG. 1B is a waveform diagram illustrating the voltages in FIG. 1A. As can be seen with reference to FIGS. 1A and 1B, during each reset event, the integration capacitor 115 is not integrating photo-current from the photodiode 110. The short durations when reset events are occurring are inconsequential at low photo-current levels, but become an important limiter of accuracy as photo-current nears maximum levels for a given application or configuration. Thus, the duration of the reset event can contribute to a loss of accuracy of the ADC function.
In-pixel ADC circuits that use synchronous sampling include a periodic clock that causes the value of voltage across the integration capacitor 115 to be compared at discrete intervals. However, if the integration capacitor 115 is simply reset to a voltage, such as a supply voltage level, errors may occur due to the loss of any charge associated with voltage in excess of the comparator threshold on the integration capacitor.